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cy7c1012av33 512 k 24 static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05254 rev. *h revised june 7, 2011 512 k 24 static ram features high speed ? t aa = 8 ns low active power ? 1080 mw (max) operating voltages of 3.3 0.3 v 2.0 v data retention automatic power-down when deselected ttl-compatible inputs and outputs easy memory expansion with ce 0 , ce 1 and ce 2 features available in non pb-free 119 ball pbga. functional description the cy7c1012av33 is a high-performance cmos static ram organized as 512 k words by 24 bits. each data byte is separately controlled by the individual chip selects (ce 0 , ce 1 , ce 2 ). ce 0 controls the data on the i/o 0 ?i/o 7 , while ce 1 controls the data on i/o 8 ?i/o 15 , and ce 2 controls the data on the data pins i/o 16 ?i/o 23 . this device has an automatic power-down feature that significantly re duces power consumption when deselected. writing the data bytes into the sram is accomplished when the chip select controlling that byte is low and the write enable input (we ) input is low. data on the respective input/output (i/o) pins is then written into the location specified on the address pins (a 0 ?a 18 ). asserting all of the chip selects low and write enable low will write all 24 bits of dat a into the sram. output enable (oe ) is ignored while in write mode. data bytes can also be individually read from the device. reading a byte is accomplished when the chip select controlling that byte is low and write enable (we ) high while output enable (oe ) remains low. under these conditions, the contents of the memory location specified on the address pins will appear on the specified data input/output (i/o) pins. asserting all the chip selects low will read all 24 bits of data from the sram. the 24 i/o pins (i/o 0 ?i/o 23 ) are placed in a high-impedance state when all the chip selects are high or when the output enable (oe ) is high during a read mode. for further details, refer to the truth table of this data sheet. the cy7c1012av33 is available in a standard 119-ball pbga. 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 512k x 24 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ?i/o 7 oe i/o 8 ?i/o 15 ce 0 , ce 1 , ce 2 we a 9 i/o 16 ?i/o 23 control logic functional block diagram [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 2 of 13 contents selection guide ................................................................ 3 pin configurations ........................................................... 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 4 ac test loads and waveforms ....................................... 5 ac switching characteristics ......................................... 5 switching waveforms ...................................................... 7 truth table ........................................................................ 9 ordering information ........................................................ 9 ordering code definitions ........................................... 9 package diagram ............................................................ 10 acronyms ........................................................................ 11 document conventions ................................................. 11 units of measure ....................................................... 11 document history page ................................................. 12 sales, solutions, and legal information ...................... 13 worldwide sales and design s upport ......... .............. 13 products .................................................................... 13 psoc solutions ......................................................... 13 [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 3 of 13 selection guide description -8 unit maximum access time 8ns maximum operating current commercial 300 ma industrial 300 maximum cmos standby current commercial/industrial 50 ma pin configurations figure 1. 119-ball pbga ( top view) [1, 2] 1234567 a ncaaaaanc b nc a a ce 0 aanc c i/o 12 nc ce 1 nc ce 2 nc i/o 0 d i/o 13 v dd v ss v ss v ss v dd i/o 1 e i/o 14 v ss v dd v ss v dd v ss i/o 2 f i/o 15 v dd v ss v ss v ss v dd i/o 3 g i/o 16 v ss v dd v ss v dd v ss i/o 4 h i/o 17 v dd v ss v ss v ss v dd i/o 5 j nc v ss v dd v ss v dd v ss dnu k i/o 18 v dd v ss v ss v ss v dd i/o 6 l i/o 19 v ss v dd v ss v dd v ss i/o 7 m i/o 20 v dd v ss v ss v ss v dd i/o 8 n i/o 21 v ss v dd v ss v dd v ss i/o 9 p i/o 22 v dd v ss v ss v ss v dd i/o 10 r i/o 23 ancncncai/o 11 t nc a a we aanc u nc a a oe aanc notes 1. nc pins are not connected on the die. 2. dnu pins have to be left floating or tied to vss to ensure proper application. [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 4 of 13 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc to relative gnd [3] ................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [3] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [3] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) .... .................................... 20 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ? c 3.3 v ? 0.3 v industrial ?40 ? c to +85 ? c dc electrical characteristics over the operating range parameter description test conditions [4] -8 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il [3] input low voltage ?0.3 0.8 v i ix input leakage current gnd < v i < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc commercial ? 300 ma industrial ? 300 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?100ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 commercial / industrial ?50ma capacitance parameter [5] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 10 pf notes 3. v il (min) = ?2.0 v for pulse durations of less than 20 ns. 4. ce refers to a combination of ce 0 , ce 1 , and ce 2 . ce is active low when all three of these si gnals are active low at the same time. 5. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 5 of 13 ac test loads and waveforms figure 2. ac test loads and waveforms [6] 90% 10% 3.3 v gnd 90% 10% all input pulses 3.3 v output 5 pf including jig and scope (a) (b) r1 317 ? r2 351 ?? rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* * capacitive load consists of all components of the test environment. ac switching characteristics over the operating range parameter [7] description -8 unit min max read cycle t power [8] v cc (typical) to the first access 1 ? ms t rc read cycle time 8 ? ns t aa address to data valid ? 8 ns t oha data hold from address change 3 ? ns t ace ce 1 , ce 2 , and ce 3 low to data valid ? 8 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [9] 1? ns t hzoe oe high to high z [9] ?5 ns t lzce ce 1 , ce 2 , and ce 3 low to low z [9] 3? ns t hzce ce 1 , ce 2 , or ce 3 high to high z [9] ?5 ns t pu ce 1 , ce 2 , and ce 3 low to power-up [10] 0? ns t pd ce 1 , ce 2 , or ce 3 high to power-down [10] ?8 ns t dbe byte enable to data valid ? 5 ns t lzbe byte enable to low z [9] 1? ns t hzbe byte disable to high z [9] ?5 ns notes 6. valid sram operation does not occur until the pow er supplies have reached the minimum operating v dd (3.0 v). as soon as 1 ms (t power ) after reaching the minimum operating v dd , normal sram operation can begin including reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. 7. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 v, input pulse levels of 0 to 3 .0 v, and output loading of the specified i ol /i oh and transmission line loads. test conditi ons for the read cycle us e output loading as show n in part (a) of the figure 2 , unless specified otherwise. 8. this part has a voltage regulator which steps down the voltage from 3 v to 2 v internally. t power time has to be provided initially before a read/write operation is started. 9. t hzoe , t hzce , t hzwe , t hzbe , and t lzoe , t lzce , t lzwe , t lzbe are specified with a load capacitance of 5 pf as in part (b) of figure 2 . transition is measured ? 200 mv from steady-state voltage. 10. these parameters are guaranteed by design and are not tested. [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 6 of 13 write cycle [11, 12] t wc write cycle time 8 ? ns t sce ce 1 , ce 2 , and ce 3 low to write end 6 ? ns t aw address set-up to write end 6 ? ns t ha address hold from write end 0 ? ns t sa address set-up to write start 0 ? ns t pwe we pulse width 6? ns t sd data set-up to write end 5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [13] 3? ns t hzwe we low to high z [13] ?5 ns t bw byte enable to end of write 6 ? ns ac switching characteristics (continued) over the operating range parameter [7] description -8 unit min max notes 11. the internal write time of the memory is defined by the overlap of ce 1 , ce 2 , and ce 3 low and we low. the chip enables must be active and we must be low to initiate a write, and the transition of any of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 13. t hzoe , t hzce , t hzwe , t hzbe , and t lzoe , t lzce , t lzwe , t lzbe are specified with a load capacitance of 5 pf as in part (b) of figure 2 on page 5 . transition is measured ? 200 mv from steady-state voltage. [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 7 of 13 switching waveforms figure 3. read cycle no. 1 [14, 15] figure 4. read cycle no. 2 (oe controlled) [15, 16, 17] figure 5. write cycle no. 1 (ce controlled) [17, 18, 19] previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data i/o notes 14. device is continuously selected. oe , ce = v il . 15. we is high for read cycle. 16. address valid prior to or coincident with ce transition low. 17. ce refers to a combination of ce 0 , ce 1 , and ce 2 . ce is active low when all three of these signals are active low at the same time. 18. data i/o is high impedance if oe = v ih . 19. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 8 of 13 figure 6. write cycle no. 2 (we controlled, oe high during write) [20, 21] figure 7. write cycle no. 3 (we controlled, oe low) [21, 23] switching waveforms (continued) t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data i/o oe note 22 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o note 22 notes 20. data i/o is high impedance if oe = v ih . 21. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. 22. during this period the i/os are in the output state and input signals should not be applied. 23. ce refers to a combination of ce 0 , ce 1 , and ce 2 . ce is active low when all three of these signals are active low at the same time. [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 9 of 13 truth table ce 0 ce 1 ce 2 oe we i/o 0 ?i/o 23 mode power h h h x x high z power-down standby (i sb ) l h h l h i/o 0 ?i/o 7 data out read active (i cc ) h l h l h i/o 8 ?i/o 15 data out read active (i cc ) h h l l h i/o 16 ?i/o 23 data out read active (i cc ) l l l l h full data out read active (i cc ) l h h x l i/o 0 ?i/o 7 data in write active (i cc ) h l h x l i/o 8 ?i/o 15 data in write active (i cc ) h h l x l i/o 16 ?i/o 23 data in write active (i cc ) l l l x l full data in write active (i cc ) l l l h h high z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 8 CY7C1012AV33-8BGC 51-85115 119-ball (14 22 2.4 mm) pbga commercial ordering code definitions temperature range: c = commercial bg = 119-ball pbga 8 = speed grade v33 = 3.3 v process technology ? 90 nm part identifier technology code: c = cmos marketing code: 7 = sram company id: cy = cypress 7 cy 1012 - bg 8 c a v33 c [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 10 of 13 package diagram figure 8. 119-ball pbga (14 22 2.4 mm) bg119, 51-85115 51-85115 *c [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 11 of 13 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor ce chip enable i/o input/output oe output enable pbga plastic ball grid array sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degree celcius mhz mega hertz a micro amperes ma milli amperes mm milli meter ms milli seconds mv milli volts mw milli watts ns nano seconds % percent pf pico farad vvolts wwatts [+] feedback
cy7c1012av33 document number: 38-05254 rev. *h page 12 of 13 document history page document title: cy7c1012av33, 512 k 24 static ram document number: 38-05254 rev. ecn no. issue date orig. of change description of change ** 113711 03/11/02 nsl new data sheet *a 117057 07/31/02 dfp removed 15-ns bin *b 117988 09/03/02 dfp added 8-ns bin *c 118992 09/19/02 dfp change cin - input capacitance -from 6 pf to 8 pf change cout -output capacitance from 8 pf to 10 pf *d 120382 11/15/02 dfp final data sheet. added note 4 to ?ac test loads and waveforms? *e 492137 see ecn nxr removed 12 ns speed bin from product offering included note #1 and 2 on page #2 changed the description of i ix from input load current to input leakage current in dc electrical characteristics table updated ordering information table *f 2896044 03/19/2010 aju updated ordering information table updated package diagram added sales, solutions, and legal information *g 3097955 11/30/2010 pras added ordering code definitions . added acronyms and units of measure . minor edits. *h 3086499 06/07/2011 aju updated selection guide (removed -10 column). updated dc electrical characteristics (removed -10 column). updated ac switching characteristics (removed -10 column). updated in new template. [+] feedback
document number: 38-05254 rev. *h revised june 7, 2011 page 13 of 13 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1012av33 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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